1. Field of the Invention
The present invention relates to a bus encoding/decoding apparatus, and more particularly, to a bus encoding/decoding apparatus and method for a low power digital signal processor (DSP) which uses a narrow data bus.
2. Description of the Related Art
As a System On a Chip (SOC) technique has been rapidly developed, various functional blocks can be installed on a single chip, and thus the chip requires a greater number of pins for interface with the outside. Since an increase in the number of pins increases the cost and power consumption of a chip, a method for efficiently using a limited number of pins is desired.
According to a narrow data bus scheme, problems caused due to lack of pins can be reduced when a decrease in performance due to wait cycles is permitted to some extent. A narrow data bus refers to a data bus having a smaller number of lines than the number of bits of data which is processed in an encoder or a decoder. Furthermore, a bus coding method, which minimizes the power consumption in the capacitance of a pin, is used to reduce the power consumption. For this method, a method for reducing transition between a current signal and a previous signal when data is transmitted via a bus, can be considered.
A bus-invert (BI) coding method and a bus inverting with transition signaling (BITS) coding method are conventional. FIGS. 1A and 1B show an encoder and a decoder, respectively, according to a BI coding method. FIGS. 2A and 2B show an encoder and a decoder, respectively, according to a BITS coding method.
The BI coding method is efficient in reducing power consumption with respect to a random data pattern, but is not efficient with respect to a data pattern such as speech or music. This is because the data pattern such as speech or music has a format of a two""s complement, for example, in the case of data of 16 bits, 0 or 1 is concentrated in the upper 8 bits.
Like the BI coding method, the BITS coding method requires an extra circuit, which determines whether to invert an extra line and data, and thus overhead becomes larger. Consequently, since the conventional coding methods for the narrow bus require an additional pin for the extra line, they restrict use of a core which is manufactured in advance.
To solve the above problem, an object of the present invention is to provide a narrow bus encoding/decoding apparatus and method for reducing interface problems with a core and reducing overhead for an additional circuit by removing the additional circuit referred to as a majority voter, which determines whether to invert data, and an extra line, which are used in the conventional BI and BITS coding methods, thereby decreasing the power consumption and the area of a chip.
To achieve the above object of the invention, there is provided an apparatus for encoding n bits of data of a data bus, including a conditional inverting unit for inverting each of (nxe2x88x921) lower bits of n data when the most significant bit of the n bits of data is 1, a storage unit for storing the last n bits of data which is output to the bus, and a first exclusive OR operating unit for performing a bitwise exclusive OR operation on the lower (nxe2x88x921) bits of the n data, which has been inverted by the conditional inverting unit, and the lower (nxe2x88x921) bits of data, which has been stored in the storage unit. The most significant bit of the n bits of data and (nxe2x88x921) bits of data, which is obtained as the result of the exclusive OR operation performed by the first exclusive OR operating unit, are output.
The conditional inverting unit is a second exclusive OR operating unit which performs an exclusive OR operation on each of the lower (nxe2x88x921) bits of the n bits of data and the most significant bit of the n bits of data.
To achieve the above object of the invention, there is also provided an apparatus for decoding n bits of encoded data of a data bus, including a storage unit for storing the lower (nxe2x88x921) bits of data of a previous encoded n bits of data which is input from the bus; a first exclusive OR operating unit for performing a bitwise exclusive OR operation on the lower (nxe2x88x921) bits of data of encoded current n bits of data, which is input from the bus following the previous n bits of data, and the lower (nxe2x88x921) bits of data, which is stored in the storage unit; and a conditional inverting unit for inverting (nxe2x88x921) bits of data, which is obtained as the result of the bitwise exclusive OR operation performed by the first exclusive OR operating unit, when the most significant bit of the current n bits of data, which is input from the bus, is 1. The most significant bit of the current n bits of data, which is input from the bus, and (nxe2x88x921) bits of data, which is obtained as the result of the inversion performed by the conditional inverting unit, are output.
The conditional inverting unit is a second exclusive OR operating unit, which performs a bitwise exclusive OR operation on the (nxe2x88x921) bits of data output from the first exclusive OR operating unit and the most significant bit of the current n bits of data in bit units.
To achieve the above object of the invention, there is provided a method for encoding n-bit data of a data bus, including the steps of (a) inverting each of (nxe2x88x921) lower bits of data when the most significant bit of the n bits of data is 1, (b) performing a bitwise exclusive OR operation on the lower (nxe2x88x921) bits of data, which has been conditionally inverted in the step (a), and the lower (nxe2x88x921) bits of data, which has last been encoded, and (c) outputting the most significant bit of the n bits of data and (nxe2x88x921) bits of data, which is obtained as the result of the exclusive OR operation.
To achieve the above object of the invention, there is also provided a method for decoding n bits of encoded data of a data bus, including the steps of (a) storing the lower (nxe2x88x921) bits of data of a previous encoded n bits of data which is input from the bus, (b) performing a bitwise exclusive OR operation on the lower (nxe2x88x921) bits of data of encoded current n bits of data, which is input from the bus following the previous n-bit data, and the lower (nxe2x88x921) bits of data, which is stored in the step (a), (c) inverting each of (nxe2x88x921) bits of data, which is obtained as the result of the bitwise exclusive OR operation, when the most significant bit of the current n bits of data, which is input from the bus, is 1, and (d) outputting the most significant bit of the current n-bit data, which is input from the bus, and (nxe2x88x921)-bit data, which is obtained as the result of the conditional inversion performed in the step (c).